#include <linux/types.h>

#ifdef DDR_RESET_REVERT
#define DDR_PARAM_150 0x00000000f0020000   //reset pad
#endif

#ifndef DDR_PARAM_018
#define _DDR_PARAM_018(v) v
#else
#define _DDR_PARAM_018(v) DDR_PARAM_018
#endif

#ifndef DDR_PARAM_1e8
#define _DDR_PARAM_1e8(v) v
#else
#define _DDR_PARAM_1e8(v) DDR_PARAM_1e8
#endif

#ifndef DDR_PARAM_1e0
#define _DDR_PARAM_1e0(v) v
#else
#define _DDR_PARAM_1e0(v) DDR_PARAM_1e0
#endif

#ifndef DDR_PARAM_150
#define _DDR_PARAM_150(v) v
#else
#define _DDR_PARAM_150(v) DDR_PARAM_150
#endif

#define DDR_PARAM(x,y) _DDR_PARAM_##x(y)

//#ifdef CONFIG_TARGET_LS2K500_EVB
#if 0
u64 ls_ddr_param[MC_REGS_COUNT] = {
	0x0300000000000000, //0x000
	0x0000000000000000, //0x008

	0x0000000000000000, //0x010
	0x4040404016100000, //0x018

	0x0201000201000000, //0x020
	0x0303000002010100, //0x028

	0x0000000003020202, //0x030
	0x0000002020056500, //0x038

	0x0201000201000000, //0x040
	0x0303000002010100, //0x048

	0x0000000003020202, //0x050
	0x0000002020056500, //0x058

	0x0201000201000000, //0x060
	0x0303000002010100, //0x068

	0x0000000003020202, //0x070
	0x0000002020056500, //0x078

	0x0201000201000000, //0x080
	0x0303000002010100, //0x088

	0x0000000003020202, //0x090
	0x0000002020056500, //0x098

	0x0201000201000000, //0x0a0
	0x0303000002010100, //0x0a8

	0x0000000003020202, //0x0b0
	0x0000002020056500, //0x0b8

	0x0201000201000000, //0x0c0
	0x0303000002010100, //0x0c8

	0x0000000003020202, //0x0d0
	0x0000002020056500, //0x0d8

	0x0201000201000000, //0x0e0
	0x0303000002010100, //0x0e8

	0x0000000003020202, //0x0f0
	0x0000002020056500, //0x0f8

	0x0201000201000000, //0x100
	0x0303000002010100, //0x108

	0x0000000003020202, //0x110
	0x0000002020056500, //0x118

	0x0201000201000000, //0x120
	0x0303000002010100, //0x128

	0x0000000003020202, //0x130
	0x00000020207f6000, //0x138

	0x0003000001ff01ff, //0x140
	0x0000000000010100, //0x148

#ifdef DDR_RESET_REVERT
	0x00000000f0020000, //0x150
#else
	0x00020000f0020000, //0x150
#endif
	0x00000000f0000000, //0x158

#ifdef USE_DDR_1TMODE
	0x0000000000010001, //0x160
#else
	0x0000000000010101, //0x160
 #endif
	0x1400000707030101, //0x168

	0x8421050084120501, //0x170
	0x0000000000000000, //0x178

	0x0000000001100000, //0x180
	0x0000000000000000, //0x188

	0x0000000000000000, //0x190
	0x0000000000000000, //0x198

	0x0000001000060d40, //0x1a0
	0x0000001000060d40, //0x1a8

	0x0000001000060d40, //0x1b0
	0x0000001000060d40, //0x1b8

	0x3030c80c03042004, //0x1c0
	0x1107070715854080, //0x1c8

	0x0a020c0402000019, //0x1d0
	0x14050c0608070406, //0x1d8

	0x0503000000000000, //0x1e0
	0x0309000000000000, //0x1e8

	0x000801e4ff050101, //0x1f0
	0x0000000004081001, //0x1f8

	0x0c000c000c000c00, //0x200
	0x0c000c0000000000, //0x208

	0x0008010e01030006, //0x210
	0x0008000b00030106, //0x218

	0x0008000b00030106, //0x220
	0x0008000b00030106, //0x228

	0x0fff000000000000, //0x230
	0x0ffffe000000ff00, //0x238

	0x0ffffe000000ff00, //0x240
	0x0ffffe000000ff00, //0x248

	0x0000000000000000, //0x250
	0x0000000000000000, //0x258

	0x0000000000000000, //0x260
	0x0000000000000000, //0x268

	0x0000001000000000, //0x270
	0x0000000000000000, //0x278

	0x0000000000000000, //0x280
	0x0000000000000000, //0x288

	0x0000000000000000, //0x290
	0x0000000000000000, //0x298

	0x0000000000000000, //0x2a0
	0x0000000000000000, //0x2a8

	0x0000000000000000, //0x2b0
	0x0000000000000000, //0x2b8

	0x0000000000000000, //0x2c0
	0x0000000000000000, //0x2c8

	0x0000000000000000, //0x2d0
	0x0000000000000000, //0x2d8

	0x0000000000000000, //0x2e0
	0x0000000000000000, //0x2e8

	0x0000000000000000, //0x2f0
	0x0000000000000000, //0x2f8

	0x0000000000000000, //0x300
	0x0000000000000000, //0x308

	0x0000000000000000, //0x310
	0x0000000000000000, //0x318

	0x0808301000016000, //0x320
	0x0000000000000000, //0x328

	0x0100011000000400, //0x330
	0x0000000000000000, //0x338

	0x0030d40000070f01, //0x340
	0x0000000000000000, //0x348

	0xffffffffffffffff, //0x350
	0x000000000001ffff, //0x358

	0x0000000000000000, //0x360
	0x0000000000000000, //0x368
};
#endif

#if defined(CONFIG_CPU_LOONGSON2K500)
u64 ls_ddr_param[MC_REGS_COUNT] = {
/* MC0_DDR3_CTRL_0x000: */	  0x0300000000000000,
/* MC0_DDR3_CTRL_0x008: */	  0x0000000000000000,
/* MC0_DDR3_CTRL_0x010: */	  0x0000000000000000,
/* MC0_DDR3_CTRL_0x018: */	  DDR_PARAM(018,0x4545454516100000),
/* MC0_DDR3_CTRL_0x020: */	  0x0201000201000000,
/* MC0_DDR3_CTRL_0x028: */	  0x0303000002010100,
/* MC0_DDR3_CTRL_0x030: */	  0x0000000003020202,
/* MC0_DDR3_CTRL_0x038: */	  0x0000002020056500,
/* MC0_DDR3_CTRL_0x040: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x048: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x050: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x058: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x060: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x068: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x070: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x078: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x080: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x088: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x090: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x098: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x0a0: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x0a8: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x0b0: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x0b8: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x0c0: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x0c8: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x0d0: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x0d8: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x0e0: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x0e8: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x0f0: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x0f8: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x100: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x108: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x110: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x118: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x120: */    0x0201000201000000,
/* MC0_DDR3_CTRL_0x128: */    0x0303000002010100,
/* MC0_DDR3_CTRL_0x130: */    0x0000000003020202,
/* MC0_DDR3_CTRL_0x138: */    0x0000002020056500,
/* MC0_DDR3_CTRL_0x140: */    0x0003000001ff01ff,
/* MC0_DDR3_CTRL_0x148: */    0x0000000000010100,
/* MC0_DDR3_CTRL_0x150: */    DDR_PARAM(150, 0x00020000f0020000),
/* MC0_DDR3_CTRL_0x158: */    0x00000000f0000000,
#ifdef USE_DDR_1TMODE
/* MC0_DDR3_CTRL_0x160: */	  0x0000000000000001,
#else
/* MC0_DDR3_CTRL_0x160: */    0x0000000000000101,
#endif
/* MC0_DDR3_CTRL_0x168: */    0x140a000707030101,
/* MC0_DDR3_CTRL_0x170: */	  0x8421050084120501,
/* MC0_DDR3_CTRL_0x178: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x180: */    0x0000000001100000,
/* MC0_DDR3_CTRL_0x188: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x190: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x198: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x1a0: */    0x0000001000060d40,
/* MC0_DDR3_CTRL_0x1a8: */    0x0000001000060d40,
/* MC0_DDR3_CTRL_0x1b0: */    0x0000001000060d40,
/* MC0_DDR3_CTRL_0x1b8: */    0x0000001000060d40,
/* MC0_DDR3_CTRL_0x1c0: */    0x3030c80c03042004,
/* MC0_DDR3_CTRL_0x1c8: */    0x1107070715854080,
/* MC0_DDR3_CTRL_0x1d0: */    0x0a020c0302000019,
/* MC0_DDR3_CTRL_0x1d8: */    0x14050c0608070406,
/* MC0_DDR3_CTRL_0x1e0: */    DDR_PARAM(1e0, 0x0503000000000000),
/* MC0_DDR3_CTRL_0x1e8: */    DDR_PARAM(1e8, 0x0309000000000000),
/* MC0_DDR3_CTRL_0x1f0: */    0x000801e4ff000101,
/* MC0_DDR3_CTRL_0x1f8: */    0x0000000004081001,
/* MC0_DDR3_CTRL_0x200: */    0x0c000c000c000c00,
/* MC0_DDR3_CTRL_0x208: */    0x0c000c0000000000,
/* MC0_DDR3_CTRL_0x210: */    0x0008010f00030006,
/* MC0_DDR3_CTRL_0x218: */    0x0008000b00030106,
/* MC0_DDR3_CTRL_0x220: */    0x0008000b00030106,
/* MC0_DDR3_CTRL_0x228: */    0x0008000b00030106,
/* MC0_DDR3_CTRL_0x230: */    0x0fff000000000000,
/* MC0_DDR3_CTRL_0x238: */    0x0ffffe000000ff00,
/* MC0_DDR3_CTRL_0x240: */    0x0ffffe000000ff00,
/* MC0_DDR3_CTRL_0x248: */    0x0ffffe000000ff00,
/* MC0_DDR3_CTRL_0x250: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x258: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x260: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x268: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x270: */    0x0000001000000000,
/* MC0_DDR3_CTRL_0x278: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x280: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x288: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x290: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x298: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2a0: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2a8: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2b0: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2b8: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2c0: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2c8: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2d0: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2d8: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2e0: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2e8: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2f0: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x2f8: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x300: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x308: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x310: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x318: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x320: */    0x0808301000016000,
/* MC0_DDR3_CTRL_0x328: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x330: */    0x0100011000000400,
/* MC0_DDR3_CTRL_0x338: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x340: */    0x0030d40000070f01,
/* MC0_DDR3_CTRL_0x348: */    0x0000000000000000,
/* MC0_DDR3_CTRL_0x350: */    0xffffffffffffffff,
/* MC0_DDR3_CTRL_0x358: */	  0x000000000001ffff,
/* MC0_DDR3_CTRL_0x360: */	  0x0000000000000000,
/* MC0_DDR3_CTRL_0x368: */	  0x0000000000000000,
};

#elif defined(CONFIG_CPU_LOONGSON2K1000)
u64 ls_ddr_param[MC_REGS_COUNT] = {
/* MC0_DDR3_CTRL_0x000: */ 0x0300000000000000,
/* MC0_DDR3_CTRL_0x008: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x010: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x018: */ DDR_PARAM(018,0x4545454516100000),
/* MC0_DDR3_CTRL_0x020: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x028: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x030: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x038: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x040: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x048: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x050: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x058: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x060: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x068: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x070: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x078: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x080: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x088: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x090: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x098: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x0a0: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x0a8: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x0b0: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x0b8: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x0c0: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x0c8: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x0d0: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x0d8: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x0e0: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x0e8: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x0f0: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x0f8: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x100: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x108: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x110: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x118: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x120: */ 0x0201000201000000,
/* MC0_DDR3_CTRL_0x128: */ 0x0303000002010100,
/* MC0_DDR3_CTRL_0x130: */ 0x0000000003020202,
/* MC0_DDR3_CTRL_0x138: */ 0x0000002020056500,
/* MC0_DDR3_CTRL_0x140: */ 0x0003000001ff01ff,
/* MC0_DDR3_CTRL_0x148: */ 0x0000000000010100,
/* MC0_DDR3_CTRL_0x150: */ DDR_PARAM(150, 0x00020000f0020000),
/* MC0_DDR3_CTRL_0x158: */ 0x00000000f0000000,
#ifdef USE_DDR_1TMODE
/* MC0_DDR3_CTRL_0x160: */ 0x0000000000010001,
#else
/* MC0_DDR3_CTRL_0x160: */ 0x0000000000010101,
#endif
/* MC0_DDR3_CTRL_0x168: */ 0x140a000707030101,
/* MC0_DDR3_CTRL_0x170: */ 0x8421050084120501,
/* MC0_DDR3_CTRL_0x178: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x180: */ 0x0000000001100000,
/* MC0_DDR3_CTRL_0x188: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x190: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x198: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x1a0: */ 0x0000001000060d30,
/* MC0_DDR3_CTRL_0x1a8: */ 0x0000001000060d30,
/* MC0_DDR3_CTRL_0x1b0: */ 0x0000001000060d30,
/* MC0_DDR3_CTRL_0x1b8: */ 0x0000001000060d30,
/* MC0_DDR3_CTRL_0x1c0: */ 0x3030c80c03042005,
/* MC0_DDR3_CTRL_0x1c8: */ 0x11070707154a4080,
/* MC0_DDR3_CTRL_0x1d0: */ 0x0a02090402000019,
/* MC0_DDR3_CTRL_0x1d8: */ 0x14050c0607070406,
/* MC0_DDR3_CTRL_0x1e0: */ DDR_PARAM(1e0, 0x0503000000000000),
/* MC0_DDR3_CTRL_0x1e8: */ DDR_PARAM(1e8, 0x0309000000000000),
/* MC0_DDR3_CTRL_0x1f0: */ 0x000801e4ff000101,
/* MC0_DDR3_CTRL_0x1f8: */ 0x0000000004081001,
/* MC0_DDR3_CTRL_0x200: */ 0x0c000c000c000c00,
/* MC0_DDR3_CTRL_0x208: */ 0x0c000c0000000000,
/* MC0_DDR3_CTRL_0x210: */ 0x0008010f00030006,
/* MC0_DDR3_CTRL_0x218: */ 0x0008000b00030106,
/* MC0_DDR3_CTRL_0x220: */ 0x0008000b00030106,
/* MC0_DDR3_CTRL_0x228: */ 0x0008000b00030106,
/* MC0_DDR3_CTRL_0x230: */ 0x0fff000000000000,
/* MC0_DDR3_CTRL_0x238: */ 0x0ffffe000000ff00,
/* MC0_DDR3_CTRL_0x240: */ 0x0ffffe000000ff00,
/* MC0_DDR3_CTRL_0x248: */ 0x0ffffe000000ff00,
/* MC0_DDR3_CTRL_0x250: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x258: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x260: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x268: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x270: */ 0x0000001000000000,
/* MC0_DDR3_CTRL_0x278: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x280: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x288: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x290: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x298: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2a0: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2a8: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2b0: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2b8: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2c0: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2c8: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2d0: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2d8: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2e0: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2e8: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2f0: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x2f8: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x300: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x308: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x310: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x318: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x320: */ 0x0808301000016000,
/* MC0_DDR3_CTRL_0x328: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x330: */ 0x0000001000000400,
/* MC0_DDR3_CTRL_0x338: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x340: */ 0x0030d40000070f01,
/* MC0_DDR3_CTRL_0x348: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x350: */ 0xffffffffffffffff,
/* MC0_DDR3_CTRL_0x358: */ 0x000000000001ffff,
/* MC0_DDR3_CTRL_0x360: */ 0x0000000000000000,
/* MC0_DDR3_CTRL_0x368: */ 0x0000000000000000,	
};
#else
#error "lose the definition of ddr_param"
#endif
